Part of the Hardware glossary:

In a shared memory multiprocessor with a separate cache memory for each processor , it is possible to have many copies of any one instruction operand : one copy in the main memory and one in each cache memory. When one copy of an operand is changed, the other copies of the operand must be changed also. Cache coherence is the discipline that ensures that changes in the values of shared operands are propagated throughout the system in a timely fashion.

There are three distinct levels of cache coherence:

  1. Every write operation appears to occur instantaneously.
  2. All processes see exactly the same sequence of changes of values for each separate operand.
  3. Different processes may see an operand assume different sequences of values. (This is considered noncoherent behavior.)
In both level 2 behavior and level 3 behavior, a program can observe stale data . Recently, computer designers have come to realize that the programming discipline required to deal with level 2 behavior is sufficient to deal also with level 3 behavior. Therefore, at some point only level 1 and level 3 behavior will be seen in machines.

This was last updated in April 2005
Posted by: Margaret Rouse

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