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clock gating

Contributor(s): Matthew Haughn

Clock gating is a power-saving feature in semiconductor microelectronics that enables switching off circuits. Many electronic devices use clock gating to turn off buses, controllers, bridges and parts of processors, to reduce dynamic power consumption.

Clock gating can be achieved either by software switching of power states per instructions in code or through smart hardware that detects whether there is work to be done and, if not, turns off the circuit. On some electronic devices, clock gating can also be achieved by a combination of methods.

Clock gating groups circuits in logical blocks that are shut off when there is no work to be done. With asynchronous circuits, the power consumption is naturally data-dependent. As the circuits are not operating at the same frequency, there is an inherent design consideration, in that some components will occasionally wait for data to do work.

Clock gating allows for synchronous circuits to emulate this data-dependant power usage with greater or lesser efficiency. With synchronous buses, extra logic circuits are required over asynchronous buses. However, synchronous circuits still retain greater simplicity and smaller size, enabling a lower cost of production. Clock gating efficiency only nears 100% when the granularity is very fine. This granularity of off-and-on control allows synchronous circuits to approach the data-dependent power efficiency of asynchronous circuits.

While clock gating is effective at reducing power required for dynamic workloads, it cannot reduce the power usage of static high workloads.  This near-100% utilization scenario is common in computing scenarios in server, rendering, mathematical and scientific computing workloads.

This was last updated in February 2016

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